In the state of the art converters from direct voltage to direct voltage or DC-DC converters are generally known; a switching converter with controller in pulse frequency mode and with a constant turn-on time is shown in FIG. 1. The converter comprises a first MOS transistor HS having a non-drivable terminal coupled to an input voltage Vin and another non-drivable terminal coupled to a terminal of an inductance L and to a non-drivable terminal of another MOS transistor LS having the other non-drivable terminal coupled to ground GND. The inductance L has its other terminal coupled to a sense resistance Rsense in turn coupled to a filter 1 constituted by a resistance ESR in series to a capacitor Cout where the resistance ESR is the parasitic resistance of the capacitor Cout; the filter 1 is placed in parallel to the load LOAD. The converter comprises a control circuit 2 having in input on the terminals CSENSEPLUS and CSENSEMINUS the current detected at the terminals of the resistance Rsense, the output voltage Vout at the terminals of the load LOAD on the input terminal VFB, a reference voltage VREF and the clock pulses MIN_FREQ coming from a timer 3; said control circuit 2 is suitable for driving the transistors HS and LS by means of the drive signals HSIDE and LSIDE through buffers 81 and 82.
In FIG. 2 the control circuit 2 is shown in more detail. Said circuit comprises a comparator 21 suitable for comparing the voltage Vout, present on the terminal VFB, with the voltage VREF, a comparator 22 having the input terminals coinciding with the terminals CSENSEPLUS and CSENSEMINUS and suitable for detecting the zero crossing of the current that flows through the inductance L and three set-reset flip-flops 23-25 in which the flip-flop 23 has the input set S coupled with the output of the comparator 21, the flip-flop 24 has the input reset R coupled with the output of the comparator 22 and the flip-flop 25 has the input set S coupled with the output of the oscillator 3. The outputs of the flip-flops 23 and 24 are respectively the drive signals HSIDE and LSIDE for the transistors HS and LS. The circuit 2 also comprises a timer 26 which when the input is at a low logic level has a low output. Initially the set reset flip-flops 23 and 25 are reset while the flip-flop 24 is set. When the signal Vout falls below the value VREF the comparator 21 sets the flip-flop 23; in this manner the signal HSIDE is raised while the signal LSIDE is lowered and the voltage Vout rises above the value of the voltage VREF. After a period given by the turn-on time Ton of the transistor HS the timer 26 changes the output signal taking it to a high logic level; said signal resets the flip-flop 23 which in turn lowers the signal HSIDE and raises the signal LSIDE. In these operating conditions, that is for loads exceeding half the ripple on the current IL in pulse width modulation, the period Tp of repetition of the charge transfer cycles in output in the converters is equal to Ton*Vin/Vout. FIG. 3 shows the time diagrams of the voltages Vout and VREF, of the current IL on the inductance L and of the signals HSIDE and LSIDE.
In the case that the load LOAD absorbs low value currents, for example of the order of milliamperes, it can happen that the current IL that flows in the inductance L becomes negative during the turn-off period Toff of the transistor HS; in this case the comparator 22 resets the flip-flop 24 so as to lower the signal LSIDE. In this manner the half-bridge constituted by the transistors LS and HS is left at high impedance to prevent the inversion of the sign of the current and the output voltage Vout is discharged on the load LOAD. When the voltage Vout falls below the value of VREF the flip-flop 24 is set and the previous cycle is repeated with the turn-on of the transistor HS; the control circuit 2 works in pulse frequency mode. The control circuit 2 can also comprise a timer 27 suitable for establishing the minimum turn-off time Toff of the transistor HS; in this manner the stability is ensured in regard to the noise induced by the switching of the transistors HS and LS.
In the case of low load and in the presence of pulse frequency modulation a charge
  Q  =                    1        2            ⁢                        Vin          -          Vout                L            ⁢              Ton        ⁡                  (                      Ton            +            Toff                    )                      =                  1        2            ⁢                        Vin          -                      V            ⁢                                                  ⁢            out                          L            ⁢              Vin        Vout            ⁢              Ton        2            is transferred at every cycle. The frequency fp of repetition of the charge transfer cycles in output in the converters is directly proportional to the current on the load Iload because fp=Q/Iload; if said current becomes low the frequency fp can return within the range of frequencies audible by humans. For this reason the converter has a device for limiting the minimum frequency; said device is implemented by the timer 3. When in the conditions of detection of negative current IL and consequent lowering of the signals HSIDE and LSIDE, the timer 3 prevents the pulse period Tp, inverse of the frequency fp, from exceeding a predefined value Tpmax by sending a pulse to the set input of the flip-flop 25 which, in turn, sends a signal on the set input of the flip-flop 24 to raise the value of the signal LSIDE. When the voltage Vout falls below the value VREF the flip-flop 25 is reset. In FIG. 4 the course of the voltage Vout, of the current IL and of the signals HSIDE, LSIDE and MIN-FREQ if the flip-flop 25 is activated can be seen.
A converter of this type suffers from an error in direct current given by half of the ripple on the output signal Vout; this comes about because the regulation is carried out on the minimum value of the voltage Vout. An integrator can be inserted whose object is to correct said error, as shown in FIG. 5. The integrator 4 comprises a transconductance amplifier 41 having the inverting input coupled to the reference voltage VREF and the non-inverting input coupled to the voltage Vout. The integrator comprises a capacitor Cint coupled between the voltage Vout and the output terminal of the amplifier 41 coupled to the control circuit 2 so that the voltage VFB is
  VFB  =                    Gm                  s          ⁢                                          ⁢          C          ⁢                                          ⁢          int                    ⁢              (                  Vout          -          Vref                )              +    Vout  where Gm is the transconductance gain of the amplifier 41. In this case the comparator 21 compares the voltage VREF with the voltage VFB. To reach the stationary state the average of the voltage Vout within a cycle must be constant. Given that the comparator PWM compares the voltage VFB with the voltage VREF the time average of the voltage VFB must also be constant and therefore Vout=VREF must be direct. The regulation that is operated on the signal VFB is on the minimum values of the signal or valley of the signal VFB.
If the load LOAD absorbs low value currents the regulation on the signal Vout is made on the average value. After a cycle of turn-on time Ton and turn-off time Toff in which the current IL goes to zero, the output voltage Vout is overloaded in relation to the value VREF. While the output voltage remains above the regulated value VREF, integrator 4 raises the voltage VFB. When the load LOAD brings the output voltage below the voltage VREF, the voltage VFB decreases until it reaches the voltage VREF and the comparator 21 is triggered, as can be seen in the time diagrams of FIG. 6.
Nevertheless it is possible that, should the converter be applied to a low load LOAD, the output voltage Vout and the current Il start to oscillate and diverge, that is the circuit results unstable. Said instability is due to the delay of the integrator; when the signal MIN_FREQ is sent, the flip-flop 25 turns on the transistor LS raising the signal LSIDE. The turn-off of the transistor LS is no longer bound to the output voltage but to the voltage VFB. The additional contribution caused by the integrator can introduce a certain delay in the turn-off of the transistor LS and thus enable the loading of a negative current of a certain value in the inductance, with consequent charge transient in the successive cycles; this can lead to the triggering of diverging oscillations on the output, as can be seen in the time diagrams of FIG. 7.